1. Field of the Invention
The present invention relates to a scrambler, and more particularly, to a parallel scrambler and a double-edge-triggered register thereof with XOR operation and a method of transforming a serial scrambler to a parallel scrambler.
2. Description of the Related Art
In the present Internet or transmission standard, such as IEEE 802.3ae or IEEE1394b, serial scramblers have been used to perform scrambling operations. FIG. 1A is a conventional transmission circuit. With reference to FIG. 1A, for a clear description, this configuration shows only the transmission part of the transmission circuit. The parallel data DATA are multiplexed into a serial data 111 by the parallel-in-serial-out circuit 110. The serial data 111 are scrambled by the serial scrambler 120 to generate the scrambled data 123. The encoder 130 further encodes the scrambled data 123, generating the encoded data 131. The transmitter 140 then transmits the data. Wherein, the serial scrambler 120 generates the serial scrambling codes by the scrambling code generator 121. The XOR gate 122 performs the XOR operation for the transmitted data and the scrambling codes.
The design of the scrambling code generator 121 varies with the transmission standards. FIG. 1B is a circuit block diagram showing a conventional IEEE 802.3ae serial scrambler. With reference to FIG. 1B, the scrambler consists D-type flip-flops, DFF1-DFF7, and xor gates. The sixth-stage output Q6 and the seventh-stage output Q7 connect to the XOR gate, the output of which fed back to the first-stage for generating the scrambling code. The scrambled data sequence is generated by the xor operation on scrambling code and input data. Accordingly, the characteristic polynomial can given by: P(x)=X7+X6+1. Every bit can be represented as: b(z)=b(z−6)⊕b(z−7), wherein Z=7,8,9. . . ∞ and b(0)˜b(6) are initial conditions.
FIG. 1C is a block diagram showing a conventional IEEE 1394b serial scrambler. With reference to FIG. 1C, except for the number of the shift registers, the structure is similar to that of IEEE 802.3ae serial scrambler. The characteristic polynomial is shown as: P(x)=X11+X9+1, in which the 11th and 9th outputs are connect to the XOR gate and generating the scrambling code.
It can be found in the structure of the serial scrambler that registers are important part of the circuit. Accordingly, the operational rate of the register has direct impact on the operational rate of the serial scrambler. Conventional registers use the single-edge-triggered mechanism. In such a mechanism, half a cycle is for storing data, and another half is used for triggering the stored data. In terms of efficiency, the single-edge-triggered mechanism wastes half a cycle for storing the data. In addition, the data rate needs to be as fast as the clock rate. If the register is operated at high speed, the clock rate should be as high. However, it is difficult to design such a clock circuit.
With the advance of semiconductor technology, the high operation speed of the circuit can be achieved. However, we cannot just rely on the advance of semiconductor technology. In addition, the circuits made by the advance semiconductor technology are so expensive that the manufacturing of such circuit is not cost-effective.